RXFIFORES=NO_IMPACT, FIFOEN=DISABLED, TXFIFORES=NO_IMPACT, RXTL=TRIGGER_LEVEL_0_1_C
FIFO Control Register. Controls USART FIFO usage and modes.
| FIFOEN | FIFO enable 0 (DISABLED): USART FIFOs are disabled. Must not be used in the application. 1 (ENABLED): Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs. |
| RXFIFORES | RX FIFO Reset 0 (NO_IMPACT): No impact on either of USART FIFOs. 1 (CLEAR): Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing. |
| TXFIFORES | TX FIFO Reset 0 (NO_IMPACT): No impact on either of USART FIFOs. 1 (CLEAR): Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing. |
| RESERVED | Reserved |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |
| RXTL | RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated. 0 (TRIGGER_LEVEL_0_1_C): Trigger level 0 (1 character or 0x01). 1 (TRIGGER_LEVEL_1_4_C): Trigger level 1 (4 characters or 0x04). 2 (TRIGGER_LEVEL_2_8_C): Trigger level 2 (8 characters or 0x08). 3 (TRIGGER_LEVEL_3_14_): Trigger level 3 (14 characters or 0x0E). |
| RESERVED | Reserved |